In several complementary metal-oxide semiconductor (CMOS) device applications, having an unsilicided silicon region (i.e., a diffusion doped resistor) or a bare silicon region without silicide (i.e., a photodetector application) is needed. In conventional approaches, silicon nitride (SiN) is often used as an optical lithographically defined hard mask. Regions with the nitride hard mask block silicidation from occurring and the electrical resistance in these regions is set by the doping level (i.e., in diffusion doped resistors).
However, the hard mask (e.g., SiN) is always left behind in such conventional flows, as removing it would also tend to roughen and remove doped silicon. In an application requiring other, or no, stacks above the silicon (i.e., photodetectors especially), this presents a problem.
Therefore, improved techniques for defining areas for silicidation in CMOS device applications would be desirable.